In a computer system such as a personal computer (PC), a central processing unit (CPU) processes massive amounts of data while accessing memory storing the data. A system memory such as of dynamic random access memory (DRAM) has a large storage capacity, but its access speed is low. In order to increase the speed of access to frequently used data, the computer system uses a cache memory (hereafter simply called “cache”) such as of static random access memory (SRAM) to be accessed by the CPU. The cache is much smaller in storage capacity but higher in access speed than the system memory like DRAM.
A cache memory has cache lines that consist of units of words of a predetermined length. A cache memory system consists of a plurality of cache lines. In the existing cache system, the line size of each cache is fixed, for example, 16 or 32 bytes. Reading (caching in) from a system memory or writing (caching out, flushing) to the system memory is performed on a line (byte) basis.
In order to maintain data coherency with the system memory, the cache system is required to cache or flush data on a line basis each time a change (write) is made to the cache line. For example, if write data from the CPU is smaller in size than the cache line, that is, if part of the cache line has to be rewritten or replaced, it will be necessary to read a complete line of data from the system memory so as to maintain the coherency of the un-replaced part of data in the cache line.
If the speed of access to the system memory is slower than the CPU and cache operating speeds, then a stall of the CPU may result. If access to the system memory occurs frequently, the data processing speed of the CPU will be reduced. Especially when processing massive amounts of data, such as color image data, the influence of a slowdown of the processing speed becomes too strong to ignore. Therefore, reducing the frequency of access to the system memory (caching or cache flushing) associated with changes (writes) to the cache can prevent the data processing speed of the CPU from slowing down.
A technique for improving the efficiency of memory access and hence processor performance is disclosed, for example, in Japanese patent application laid-open No H11-65925 (65925/1999),incorporated herein by reference. This publication, however, does not disclose a technique for reducing the number of access operations to a system memory associated with changes (writes) to the cache.